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IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI 9 Amp Low-Side Ultrafast MOSFET Driver Features
* Built using the advantages and compatibility of CMOS and IXYS HDMOSTM processes. * Latch Up Protected * High Peak Output Current: 9A Peak * Operates from 4.5V to 25V * Ability to Disable Output under Faults * High Capacitive Load Drive Capability: 2500pF in <15ns * Matched Rise And Fall Times * Low Propagation Delay Time * Low Output Impedance * Low Supply Current
General Description
The IXDD409/IXDI409/IXDN409 are high speed high current gate drivers specifically designed to drive the largest MOSFETs and IGBTs to their minimum switching time and maximum practical frequency limits. The IXDD409/IXDI409/ IXDN409 can source and sink 9A of peak current while producing voltage rise and fall times of less than 30ns. The input of the drivers are compatible with TTL or CMOS and are fully immune to latch up over the entire operating range. Designed with small internal delays, cross conduction/ current shoot-through is virtually eliminated in the IXDD409/ IXDI409/IXDN409. Their features and wide safety margin in operating voltage and power make the drivers unmatched in performance and value. The IXDD409 incorporates a unique ability to disable the output under fault conditions. When a logical low is forced into the Enable input, both final output stage MOSFETs (NMOS and PMOS) are turned off. As a result, the output of the IXDD409 enters a tristate mode and achieves a Soft TurnOff of the MOSFET/IGBT when a short circuit is detected. This helps prevent damage that could occur to the MOSFET/ IGBT if it were to be switched off abruptly due to a dv/dt overvoltage transient. The IXDN409 is configured as a non-inverting gate driver, and the IXDI409 is an inverting gate driver. The IXDD409/IXDI409/IXDN409 are available in the standard 8pin P-DIP (PI), SOP-8 (SI), 5-pin TO-220 (CI) and in the TO-263 (YI) surface-mount packages.
Applications
* * * * * * * * * * Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters Pulse Transformer Driver Limiting di/dt under Short Circuit Class D Switching Amplifiers
Figure 1A - IXDD409 Functional Diagram
Ordering Information
Part Number IXDD409PI IXDD409SI IXDD409YI IXDD409CI IXDI409PI IXDI409SI IXDI409YI IXDI409CI IXDN409PI IXDN409SI IXDN409YI IXDN409CI Package Type 8-Pin PDIP 8-Pin SOIC 5-Pin TO-263 5-Pin TO-220 8-Pin PDIP 8-Pin SOIC 5-Pin TO-263 5-Pin TO-220 8-Pin PDIP 8-Pin SOIC 5-Pin TO-263 5-Pin TO-220 Temp. Range Configuration Non Inverting With Enable Line
-40C to +85C
-40C to +85C
Inverting
Figure 1B - IXDN409 Functional Diagram
-40C to +85C
Non Inverting
Figure 1C - IXDI409 Functional Diagram
Copyright (c) IXYS CORPORATION 2002 Patent Pending
First Release
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Absolute Maximum Ratings (Note 1)
Parameter
Supply Voltage All Other Pins Power Dissipation, TAMBIENT 25 oC 8 Pin PDIP (PI) 8 Pin SOIC (SI) TO220 (CI), TO263 (YI) Derating Factors (to Ambient) 8 Pin PDIP (PI) 8 Pin SOIC (SI) TO220 (CI), TO263 (YI) Storage Temperature Lead Temperature (10 sec)
Operating Ratings
Parameter
Maximum Junction Temperature Operating Temperature Range Thermal Impedance (Junction To Case) TO220 (CI), TO263 (YI) (JC)
Value
25 V -0.3 V to VCC + 0.3 V 975mW 1055mW 17W 7.6mW/oC 8.2mW/oC 0.14W/oC -65 oC to 150 oC 300 oC
Value
150 oC -40 oC to 85 oC 0.95 oC/W
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 4.5V VCC 25V . All voltage measurements with respect to GND. IXDD409 configured as described in Test Conditions.
Symbol VIH VIL VIN IIN VOH VOL ROH ROL IPEAK IDC VEN VENH VENL tR tF tONDLY tOFFDLY tENOH tDOLD VCC ICC
Parameter High input voltage Low input voltage Input voltage range Input current High output voltage Low output voltage Output resistance @ Output high Output resistance @ Output Low Peak output current Continuous output current Enable voltage range High En Input Voltage Low En Input Voltage Rise time Fall time On-time propagation delay Off-time propagation delay Enable to output high delay time Disable to output low Disable delay time Power supply voltage Power supply current
Test Conditions
Min 3.5
Typ
Max 0.8
Units V V V A V
-5 0V VIN VCC -10 VCC - 0.025
VCC + 0.3 10
0.025 IOUT = 10mA, VCC = 18V IOUT = 10mA, VCC = 18V VCC is 18V Limited by package power dissipation IXDD409 Only IXDD409 Only IXDD409 Only CL=2500pF Vcc=18V CL=2500pF Vcc=18V CL=2500pF Vcc=18V CL=2500pF Vcc=18V IXDD409 Only, Vcc=18V IXDD409 Only, Vcc=18V 4.5 VIN = 3.5V VIN = 0V VIN = + VCC 18 1 0 8 8 33 31 10 10 36 33 0.8 0.8 9 2 - .3 2/3 Vcc 1/3 Vcc 15 15 40 36 52 30 25 3 10 10 Vcc + 0.3 1.5 1.5
V A A V V V ns ns ns ns ns ns V mA A A
Specifications Subject To Change Without Notice
2
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Pin Configurations
1 VCC 2 IN 3 EN * 4 GND
VCC 8 OUT 7 OUT 6 GND 5
1 2 3 4 5
Vcc OUT GND IN EN *
8 PIN DIP (PI) SO8 (SI)
TO220 (CI) TO263 (YI)
Pin Description
SYMBOL VCC IN EN * OUT FUNCTION Supply Voltage Input Enable Output DESCRIPTION Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 25V. Input signal-TTL or CMOS compatible. The system enable pin. This pin, when driven low, disables the chip, forcing high impedance state to the output (IXDD409 Only). Driver Output. For application purposes, this pin is connected, through a resistor, to Gate of a MOSFET/IGBT. The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance.
GND
Ground
* This pin is used only on the IXDD409, and is N/C on the IXDI409 and IXDN409. Note 1: Operating the device beyond parameters with listed "absolute maximum ratings" may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component.
Figure 2 - Characteristics Test Diagram
VIN
3
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Typical Performance Characteristics
Fig. 3
40 35 25 30 Rise Time (ns) 11900 pF 8900 pF 5860 pF 2950 pF 1500 pF 5 0 8 9 10 11 12 13 14 15 16 17 18 Supply Voltage (V) 5 Fall Times (ns) 25 20 15 10 20 11900 pF 8900 pF 5860 pF 10 2950 pF 1500 pF
Rise Tim vs. Supply Voltage es
Fig. 4
30
Fall Times vs. Supply Voltage
15
0 8 9 10 11 12 13 14 15 16 17 18 Supply Voltage (V)
Fig. 5
12
Rise And Fall Times vs. Temperature CL=2500pF, Vcc=18V
Fig. 6
35
Rise Time vs. Load Capacitance
8V
10
Ri t me se i
30
10V 12V 14V 16V 18V
8
Fal t me li
25 Rise time (ns)
25 Tem perature 40 60 85
6
20
4
15
2
10
0 -40 -20 0
5 1.35
2.7
5.4 Load Capacitance
8.1
10.8
Fig. 7
25
Fall Time vs. Load Capacitance
Fig. 8
3.5
Max / Min Input vs. Temperature
8V
23
10V
21 19 Fall Time (ns) 17 15 13 11 9 7 5 1.35
3 Maximum Input High 2.5 Max / Min Input (V) 2 1.5 Minimum Input Low 1 0.5 0 -40
12V 14V 16V 18V
2.7
5.4 Load Capacitance (nF)
8.1
10.8
-20
0
25 Temperature
40
60
85
4
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI
Fig. 9
1000
Supply Current vs. Load Capacitance Vcc = 18V
Fig. 10
1000
S upply C urrent vs. F requency V cc = 18V
10800 pF 8100 pF 5400 pF 2700 pF 100
100
2M z H
Supply Current (mA)
1350 pF
Supply Current (mA)
1M z H 500kH z 10 100kH z 50kH z 1
10
10kH z
1
0.1 1000
0.1
10000
1
10
100
1000
Load C apacitance (pF)
Frequenc y (kHz)
Fig. 11
1000
SupplyCurrent vs. Load Capacitance Vcc =12V
Fig. 12
1000
Supply Current vs. Frequency Vcc = 12V
10800 pF 8100 pF 5400 pF 2700 pF 1350 pF
100 100
Supply Current (mA)
Supply Current (mA)
2M z H 1M z H 10 500kH z
10
1
100kH z 50kH z 1 10kH z
0.1
0.1 1000
0.01 10000 1 10 100 1000 10000
Load C apacitance (pF)
Frequency (kHz)
Fig. 13
1000
SupplyCurrent vs. Load Capacitance Vcc = 8V
Fig. 14
1000
Supply Current vs. Frequency Vcc = 8V
100
100
10800 pF 8100 pF 5400 pF 2700 pF 1350 pF
Supply Current (mA)
2M z H 1M z H 10 500kH z
Supply Current (mA)
10000
10
1
100kH z 1 50kH z
0.1 10kH z 0.1 1000 0.01 1 10 100 1000 10000
Load Capacitance (pF)
Frequency (kHz)
5
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI
Fig. 15
50 48 46 Propagation Delay (ns)
Propagation Delayvs. Supply Voltage
Fig. 16
50 48 46 Propagation Delay (ns) 44 42 40 38 36 34
Propagation Delayvs. Input Voltage
44 42 40 38 36 34 32 30 8 9 10 11 12 13 14 15 16 17 18 Supply Voltage (V)
Toffdly(D 409, D 409) D N Tondly (D I409) Tondly (D 409, D 409) D N Toffdly (D I409)
Tondly (DD409, DN409) Toffdly (DI409)
Toffdly (DD409, DN409) Tondly (DI409)
32 30 3 4 5 6 7 8 9 10 11 12 Input Voltage (V)
Fig. 17
45 40 35 30 Time (ns) 25 20 15 10 5 0 -40
Propagation Delay Times vs. Junction Temperature
Fig. 18
0.6
Quiescent Supply Current vs. Junction Temperature Vcc=18v Vin=5v@1kHz
Quiescent Supply Current (mA) 25 Temperature (C) 40 60 85
Tondly (DD409, DN409) Toffdly (DI409)
0.5
0.4
Toffdly (DD409, DN409) Tondly (DI409)
0.3
0.2
0.1
-20
0
0 -40
-20
0
25 Temperature (C)
40
60
85
Fig. 19
0
Vcc vs. P Channel Peak Output Current CL = 10 nF
Fig. 20
20 18
Vcc vs. NChannel Peak O utput Current CL=10 nF
P Channel Peak Output Current (A)
-2
N Channel Peak Output Current (A)
5 7.5 10 12.5 15 17.5 20 22.5 25
16 14 12 10 8 6 4 2
-4
-6
-8
-10
-12
-14
0 5 7.5 10 12.5 15 17.5 20 22.5 25
Vcc (V)
Vcc (V)
6
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI
Fig. 21
10 9.8
PChannel O Current vs. T perature utput em Vcc =18VCL=10 nF
Fig. 22
15 14.5
NChannel Peak O Current vs. T perature uput em Vcc =18VCL =10nF
P Channel Output Current (A)
N Channel Output Current (A)
9.6 9.4 9.2 9 8.8 8.6 8.4 8.2 8 -60
14 13.5 13 12.5 12 11.5 11 10.5 10 -60
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
T perature (C em )
T perature (C em )
Fig. 23
1.6 High State Output Resistance (Ohms) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 5
High State Output Resistance vs. Supply Voltage
Fig. 24
1.2
Low State Output Resistance vs. Supply Voltage
Low State Output Resistance (Ohms) 7.5 10 12.5 15 17.5 20 22.5 25
1
0.8
0.6
0.4
0.2
0 5 7.5 10 12.5 15 17.5 20 22.5 25 Supply Voltage (V) Supply Voltage (V)
Figure 25 - Typical Application Short Circuit di/dt Limit
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IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET module such as the VM0580-02F, (580A, 200V), as shown in Figure 25, can cause the current through the module to flow in excess of 1500A for 10s or more prior to self-destruction due to thermal runaway. For this reason, some protection circuitry is needed to turn off the MOSFET module. However, if the module is switched off too fast, there is a danger of voltage transients occuring on the drain due to Ldi/dt, (where L represents total inductance in series with drain). If these voltage transients exceed the MOSFET's voltage rating, this can cause an avalanche breakdown. The IXDD409 has the unique capability to softly switch off the high-power MOSFET module, significantly reducing these Ldi/dt transients. Thus, the IXDD409 helps to prevent device destruction from both dangers; over-current, and avalanche breakdown due to di/dt induced over-voltage transients. The IXDD409 is designed to not only provide 9A under normal conditions, but also to allow it's output to go into a high impedance state. This permits the IXDD409 output to control a separate weak pull-down circuit during detected overcurrent shutdown conditions to limit and separately control dVGS/dt gate turnoff. This circuit is shown in Figure 26. Referring to Figure 26, the protection circuitry should include a comparator, whose positive input is connected to the source of the VM0580-02. A low pass filter should be added to the input of the comparator to eliminate any glitches in voltage caused by the inductance of the wire connecting the source resistor to ground. (Those glitches might cause false triggering of the comparator). The comparator's output should be connected to a SRFF(Set Reset Flip Flop). The flip-flop controls both the Enable signal, and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with 18 VDC being the maximum allowable limit). A low power MOSFET, such as the 2N7000, in series with a resistor, will enable the VMO580-02F gate voltage to drop gradually. The resistor should be chosen so that the RC time constant will be 100us, where "C" is the Miller capacitance of the VMO580-02F. For resuming normal operation, a Reset signal is needed at the SRFF's input to enable the IXDD409 again. This Reset can be generated by connecting a One Shot circuit between the IXDD409 Input signal and the SRFF restart input. The One Shot will create a pulse on the rise of the IXDD409 input, and this pulse will reset the SRFF outputs to normal operation. When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected between the MOSFET Source and ground, increases. This triggers the comparator at a preset level. The SRFF drives a low input into the Enable pin disabling the IXDD409 output. The SRFF also turns on the low power MOSFET, (2N7000). In this way, the high-power MOSFET module is softly turned off by the IXDD409, preventing its destruction.
Figure 26 - Application Test Diagram
+
Ld 10uH
-
VB
IXDD409 VCC VCCA IN EN
+ -
Rd 0.1ohm Rg OUT Rsh 1600ohm 1ohm
High_Power VMO580-02F
VCC
+ -
VIN
GND SUB Rs Low_Power 2N7002/PLP R+ 10kohm Ls 20nH
One ShotCircuit Rcomp 5kohm NOT1 CD4049A Ros 1Mohm Cos 1pF Q R REF NAND CD4011A NOT2 CD4049A Ccomp 1pF 0 Comp LM339 + V+ V+ -
C+ 100pF
NOT3 CD4049A EN
NOR1 CD4001A
S
NOR2 CD4001A
SR Flip-Flop
8
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI
Supply Bypassing and Grounding Practices, Output Lead inductance
When designing a circuit to drive a high speed MOSFET utilizing the IXDD409/IXDI409/IXDN409, it is very important to keep certain design criteria in mind, in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXDD409 to charge a 5000pF capacitive load from 0 to 25 volts in 25ns... Using the formula: I= V C / t, where V=25V C=5000pF & t=25ns we can determine that to charge 5000pF to 25 volts in 25ns will take a constant current of 5A. (In reality, the charging current won't be constant, and will peak somewhere around 8A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXDD409 must be able to draw this 5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXDD409 to an absolute minimum. GROUNDING In order for the design to turn the load off properly, the IXDD409 must be able to drain this 5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path #1 is between the IXDD409 and it's load. Path #2 is between the IXDD409 and it's power supply. Path #3 is between the IXDD409 and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, (for instance), the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXDD409. OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and it's load as short and wide as possible. If the driver must be placed farther than 2" from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connect directly to the ground terminal of the load.
TTL to High Voltage CMOS Level Translation (IXDD409 Only)
The enable (EN) input to the IXDD409 is a high voltage CMOS logic level input where the EN input threshold is 1/2 VCC, and may not be compatible with 5V CMOS or TTL input levels. The IXDD409 EN input was intentionally designed for enhanced noise immunity with the high voltage CMOS logic levels. In a typical gate driver application, VCC =15V and the EN input threshold at 7.5V, a 5V CMOS logical high input applied to this typical IXDD409 application's EN input will be misinterpreted as a logical low, and may cause undesirable or unexpected results. The note below is for optional adaptation of TTL or 5V CMOS levels. The circuit in Figure 27 alleviates this potential logic level misinterpretation by translating a TTL or 5V CMOS logic input to high voltage CMOS logic levels needed by the IXDD409 EN input. From the figure, VCC is the gate driver power supply, typically set between 8V to 20V, and VDD is the logic power supply, typically between 3.3V to 5.5V. Resistors R1 and R2 form a voltage divider network so that the Q1 base is positioned at the midpoint of the expected TTL logic transition levels. A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to the Q1 emitter will drive it on. This causes the level translator output, the Q1 collector output to settle to VCESATQ1 + VTTLLOW=<~2V, which is sufficiently low to be correctly interpreted as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given in the IXDD409 data sheet.) A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high, V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in Figure 27 will cause Q1 to be biased off. This results in Q1 collector being pulled up by R3 to VCC=15V, and provides a high voltage CMOS logic high output. The high voltage CMOS logical EN output applied to the IXDD409 EN input will enable it, allowing the gate driver to fully function as an 8 Amp output driver. The total component cost of the circuit in Figure 27 is less than $0.10 if purchased in quantities >1K pieces. It is recommended that the physical placement of the level translator circuit be placed close to the source of the TTL or CMOS logic circuits to maximize noise rejection.
Figure 27 - TTL to High Voltage CMOS Level Translator
CC (From Gate Driver Power Supply)
10K
R3
V DD (From Logic Power Supply)
3.3K
R1 Q1 2N3904
(To IXDD409 EN Input)
High V oltage CMOS EN Output
3.3K
R2
or TTL Input)
9
IXDD409PI / 409SI / 409YI / 409CI IXDI409PI / 409SI / 409YI / 409CI IXDN409PI / 409SI / 409YI / 409CI Package Information
NOTE: Mounting or solder tabs on all packages are connected to ground
IXYS Corporation 3540 Bassett St; Santa Clara, CA 95054 Tel: 408-982-0700; Fax: 408-496-0670 www.ixys.com e-mail: sales@ixys.net
IXYS Semiconductor GmbH Edisonstrasse15 ; D-68623; Lampertheim Tel: +49-6206-503-0; Fax: +49-6206-503627 e-mail: marcom@ixys.de
Directed Energy, Inc. An IXYS Company 2401 Research Blvd. Ste. 108 Ft. Collins, CO 80526 Tel: 970-493-1901; Fax: 970-493-1903 www.directedenergy.com e-mail: deiinfo@directedenergy.com
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Doc #9200-0252 R1

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